1. Field of the Invention
The present invention relates to a method of forming a patterned hard mask layer, and more particularly, to a method of forming a patterned hard mask layer on an amorphous silicon layer with improved alignment accuracy.
2. Description of the Prior Art
The development of semiconductor integrated circuit technology progresses continuously and circuit designs in products of the new generation become smaller and more complicated than those of the former generation. The amount and the density of the functional devices in each chip region are increased constantly according to the requirements of innovated products, and the size of each device has to become smaller accordingly. Photolithography technology is used to form patterned structures in general semiconductor manufacturing processes. The size and the spacing between the patterned structures are limited by the exposure resolution minimum of the traditional photolithography technology and hard to be further shrunk. Therefore, many approaches such as the sidewall image transfer (SIT) technology and the multiple patterning have been provided by the related industries for forming patterned structures in the advanced manufacturing process. However, there are more layers stacked before the lithography process applying the SIT technology, and it becomes more difficult to measure alignment marks under the stacked layers. The alignment accuracy may be seriously influenced accordingly.